1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device having a function which allows a disturb test with good timing accuracy by a low-speed tester.
2. Description of the Background Art
A disturb test is a kind of known test for semiconductor memory devices. In the disturb test, a series of operations is performed as follows. A word line is raised to read out data in a memory cell onto a bit line. The data thus read is amplified by a sense amplifier, and is rewritten into the memory cell, and the word line is lowered. By the above operations, a memory cell on a neighboring unselected word line is disturbed.
In a conventional semiconductor memory device, an output (high-frequency signal) of an oscillator circuit arranged within the device is used as a trigger signal of the disturb test in order to use a low-speed tester for a short-cycle test, in which a period of each series of operations for the disturb test is reduced.
However, an influence by a process and test environments such as a temperature and a humidity cause variations in timing accuracy of the high-frequency signal forming the trigger. This results in a problem that the test cannot be performed accurately.
A testing burn-in apparatus which can test a large number of devices at a time may be used as the low-speed tester. In this case, the acceptance/rejection determination is performed in a scanning manner so that a long time is required for determining all the devices.
During the testing, a large number of devices are disturbed at a time so that the temperature in a burn-in tank rises, resulting in a strict environment for the devices. Accordingly, the device may enter an overtest specification state while the acceptance/rejection determination is being performed. This results in a problem that an acceptable device may be rejected depending on a margin.